This application claims the priority of Korean Patent Application No. 2002-85866, filed Dec. 28, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a control circuit which controls a bitline coupling capacitor.
2. Description of the Related Art
As the integration density of semiconductor memory devices, such as DRAMs, increases, the area of memory cells decreases, and the capacitance of a storage capacitor in a DRAM memory cell, i.e., cell capacitance, also decreases, which affects the operational characteristics of the DRAM, such as sensing speed or refresh, and leads to deterioration of the DRAM's performance.
In general, in order to solve the aforementioned problems, a bitline coupling scheme has been used. FIG. 1 is a circuit diagram of a semiconductor memory device having a conventional bitline coupling scheme. Referring to FIG. 1, a bitline BL is connected to an end of a coupling capacitor 12, and a control signal PBLC is applied to the other end of the coupling capacitor 12. The bitline BL and a complementary bitline BLB are connected to a memory cell array 11 including memory cells MC0, . . . , MCn. A sensing amplifier 13 senses a difference ΔVBL in the voltage between the bitline BL and the complementary bitline BLB and amplifies the voltage difference.
The control signal PBLC is generated by a control circuit 14. When the control signal PBLC has a logic value of ‘1’, the coupling capacitor 12 connected to the bitline BL starts to operate so that the capacitance of a storage capacitor C in a memory cell MC, i.e., cell capacitance, increases.
The control circuit 14 includes a NAND gate ND1, which receives a block selection signal BI and a signal (PBLCE) enabling a bitline coupling scheme, and an inverter I1, which generates the control signal PBLC by inverting an output signal of the NAND gate ND1.
As shown in FIG. 1, however, in the conventional bitline coupling scheme, an external power supply VDD is applied to a source and a bulk of a PMOS transistor P1 of the inverter I1. Accordingly, as the level of the external power supply VDD increases, the voltage level of the control signal PBLC increases. Thus, in a case where data stored in the memory cell have a logic value of ‘1’, the voltage difference ΔVBL between the bitline BL and the complementary bitline BLB increases. As a result, the sensing speed of the sensing amplifier 13 increases, and the performance of the semiconductor memory device improves.
On the other hand, if the data stored in the memory cell have a logic value of ‘0’, the voltage difference ΔVBL between the bitline BL and the complementary bitline BLB decreases even when the level of the external power supply VDD increases. Accordingly, the sensing speed of the sensing amplifier 13 decreases, and the performance of the semiconductor memory device deteriorates.